The present invention relates to an FET logic circuit for processing a digital signal in a communication apparatus, a computer and others, and more particularly to an FET logic circuit which is suited to fabricate an integrated logic circuit using GaAs.MESFET device technology.
With the up-grading in the processing speed of a digital signal in a communication apparatus, a computer, a measuring instrument and others, it becomes necessary to realize a high-speed logic circuit. Thus, an ultra-high-speed integrated logic circuit has been earnestly developed which is formed of the so-called MES field effect transistors (namely, MESFET's) utilizing the Schottky barrier between a metal and a compound semiconductor such as GaAs, and some of such MESFET integrated logic circuits are now available on the market. However, it is difficult to replace an actually-used integrated logic circuit which is constituted of silicon bipolar transistors, by a GaAs MESFET integrated logic circuit, for the reasons that a field effect transistor is different in operation principle from a bipolar transistor and characteristics of the field effect transistor vary widely.
FIG. 2 shows the fundamental configuration of a conventional logic circuit including GaAs MESFET's (Technical Report of the Institute of Electronics and Communication Engineers of Japan, SSD86-46, pages 40 and 41). The logic circuit of FIG. 2 is usually called "source coupled logic". Referring to FIG. 2, the gate electrodes of FET's 11 and 12 are connected to a positive phase input terminal 3 and a negative phase input terminal 4, respectively, and the drain electrode of the FET 11 is connected to a ground terminal 1 through a diode 6. Further, the source electrodes of the FET's 11 and 12 are not only connected to each other, but also connected to a negative voltage terminal 2 through a resistor 6. A series combination of resistors 7 and 8 is connected in parallel to the diode 6, and the connecting point of the resistors 7 and 8 is connected to the drain electrode of the FET 12 through a resistor 9. The gate electrode of an FET 13 is connected to the drain electrode of the FET 12, and the source and drain electrodes of the FET 13 are connected to the ground terminal 1 and an output terminal 5, respectively. It is to be noted that the diode 6 and the resistors 7 to 9 are connected as shown in FIG. 2 to match the high level of the output signal of this logic circuit with the operating condition of the input/output interface circuit of a conventional emitter coupled logic. Now, let us express a voltage applied across the diode 6, the resistance values of the resistors 7 and 8, the threshold voltage of the FET 13, the mutual conductance factor of the FET 13 and an output current by V.sub.f, R.sub.1, R.sub.2, V.sub.th, K.sub.o and I.sub.OH, respectively. Then, the high level V.sub.OH of the output voltage appearing on the terminal 5 is given by the following equation: ##EQU1##
As is evident from the equation (1), the high level of the output voltage is a single-valued function of the threshold voltage V.sub.th of the FET 13. That is, the high level of the output voltage varies in proportion to a change in threshold voltage V.sub.th. Variations in threshold voltage of a GaAs MESFET due to the manufacturing condition are so great that it is very difficult to replace an actually-used emitter coupled logic by a source coupled logic which includes GaAs.MESFETs.